The following pseudo-records describe the bit masks supported by the register command where "*" represents reserved bits with no corresponding name:
| EFL | record | *:13, AC:1, VM:1, RF:1, *:1, NT:1, IOPL:2, OF:1, DF:1, IF:1, TF:1, SF:1, ZF:1, *:1, AF:1, *:1, PF:1, *:1, CF:1 |
| CR0 | record | PG:1, CD:1, NW:1, *:10, AM:1, *:1, WP:1, *:10, NE:1, ET:1, TS:1, EM:1, MP:1, PE:1 |
| PTE | record | FRM:20, PTE_AVL:3, *:2, PTE_D:1, PTE_A:1, PTE_CE:1, PTE_WT:1, PTE_US:1, PTE_RW:1, PTE_P:1 |
| SEL | record | SEL:13, TI:1, PL:2 |
| DR6 | record | *:16, BT:1, BS:1, BD:1, *:9, B3:1, B2:1, B1:1, B0:1 |
| DR7 | record | LEN3:2, RW3:2, LEN2:2, RW2:2, LEN1:2, RW1:2, LEN0:2, RW0:2, *:2, GD:1, *:3, GE:1, LE:1, G3:1, L3:1, G2:1, L2:1, G1:1, L1:1, G0:1, L0:1 |
| TR4 | record | TR4_TAG:21, TR4_WVAL:1, TR4_LRU:3, TR4_RVAL:4, *:3 |
| TR5 | record | *:21, TR5_SSEL:7, TR5_ESEL:2, TR5_CTL:2 |
| TR6 | record | FRM:20, TR6_V:1, TR6_D:1, TR6_DP:1, TR6_U:1, TR6_UP:1, TR6_W:1, TR6_WP:1, *:4, TR6_C:1 |
| TR7 | record | FRM:20,*:7, TR7_HT:1, TR7_REP:2, *:2 |